The invention pertains to semiconductor processing methods wherein dopant is out-diffused into both n-type and p-type doped regions of a semiconductive material. In particular aspects, the invention pertains to methods of forming n-well and p-well contacts.
Modern semiconductive processing methods frequently involve formation of n-type diffusion regions and p-type diffusion regions in a semiconductive material, as well as formation of transistors associated with the n-type diffusion regions and p-type diffusion regions. Monocrystalline silicon wafers are commonly utilized as semiconductive substrates, with the wafers generally being lightly background doped with p-type conductivity-enhancing dopant. At various regions within a wafer, an n-type conductivity-enhancing dopant can be implanted to a concentration which overwhelms the p-type dopant to thereby form n-wells. In other regions of the wafer the n-type dopant is not implanted, and such other regions remain as p-type regions (which can be referred to as p-wells).
Complementary metal-oxide semiconductors (CMOS) can be formed utilizing the n-wells and p-wells of the semiconductive wafer. Specifically, the n-wells are utilized for formation of p-channel metal-oxide semiconductor (PMOS) field effect transistors, and the p-wells are utilized for formation of n-channel metal-oxide semiconductor (NMOS) field effect transistors. In particular constructions, the n-well is generally held to Vcc through a tie-down contact, and the p-well to Vbb through a tie-down contact. The CMOS is typically formed at the periphery of memory array circuitry, and accordingly is referred to as peripheral circuitry.
A peripheral circuitry fragment 10 is shown and described with reference to FIG. 1. More specifically, fragment 10 comprises a semiconductor substrate 11, having a peripheral region 12. Peripheral region 12 comprises a PMOS transistor region 14 (also called a PMOS region), NMOS transistor region 16 (also called an NMOS region), n-well tie-down region 18, and p-well tie-down region 20. It is noted that PMOS transistor region 14 and n-well tie-down region 18 are comprised by an n-well (i.e., a lightly n-type doped region) of a semiconductor substrate, whereas NMOS transistor region 16 and p-well tie-down region 20 are comprised by a p-well (i.e., a lightly p-type doped region) of the semiconductor substrate.
To aid in interpretation of this disclosure and the claims that follow, the terms xe2x80x9csemiconductive substratexe2x80x9d and xe2x80x9csemiconductor substratexe2x80x9d are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Generally, the substrate will comprise a semiconductive material, such as, for example, monocrystalline silicon, lightly doped with a background p-type dopant. Accordingly, p-well regions comprise portions of the substrate simply containing the background dopant, and n-well regions comprise portions of the substrate wherein n-type conductivity-enhancing dopant is provided to a concentration sufficient to overwhelm the background p-type doping. The background p-type doping can be provided to a concentration of, for example, from about 1xc3x971015 atoms/cm3 to about 5xc3x971015 atoms/cm3, and the n-type dopant provided to form the n-wells can be provided to a concentration of, for example, about 1xc3x971016 atoms/cm3.
Transistor gates 22 and 24 are formed over PMOS transistor region 14 and NMOS transistor region 16, respectively. Transistor gates 22 and 24 can comprise, for example, a stack of polysilicon and silicide over gate oxide.
Sidewall spacers 26 are provided adjacent the gate stacks. Sidewall spacers 26 generally comprise insulative materials, such as, for example, silicon dioxide or silicon nitride.
Heavily doped p-type source/drain regions 28 are provided proximate gate 22, and heavily doped n-type source/drain regions 30 are provided proximate gate 24 (with the term xe2x80x9cheavily dopedxe2x80x9d meaning a dopant concentration of greater than or equal to 1019 atoms/cm3. Also, n-type halo regions 32 are provided adjacent PMOS source/drain regions 28, and p-type halo regions 34 are provided adjacent NMOS source/drain regions 30. LDD regions (not shown) would also typically be provided proximate one or both of transistor gates 22 and 24.
Transistor gate 24 and the diffusion regions proximate thereto define an NMOS transistor 25, and transistor gate 22 and the diffusion regions proximate thereto define a PMOS transistor 27.
Trench isolation regions 36 and 38 are provided within p-well tie-down region 20 and n-well tie-down region 18, respectively. Isolation regions 36 and 38 can comprise, for example, shallow trench isolation regions, with the shallow trenches being filled with silicon dioxide. A heavily doped p-type diffusion region 40 is formed within p-well tie-down region 20, and a heavily n-type doped diffusion region 42 is formed within n-well tie-down region 18. Regions 40 and 42 define a p-well tie-down node and an n-well tie-down node, respectively. The tie-down regions are formed at the same time as the source/drain regions for devices, and are formed using the same masks and implants.
An insulative material 44 extends over regions 14, 16, 20 and 18. Material 44 can comprise, for example, a stack of borophosphosilicate glass (BPSG) on an oxide (which functions as a barrier). Openings extend through insulative material 44 to diffusion regions 28, 30, 40 and 42 (only portions of the openings over regions 28 and 30 are shown), and a conductive material 46 is formed within such openings to form electrical contact to the underlying diffusion regions. The material 46 in the n-well and p-well tie-down regions 18 and 20 forms conductive plugs 47 and 49, respectively. Conductive material 46 can comprise, for example, a metal (such as tungsten or aluminum), with a liner (an exemplary liner is TiN).
Conductive material 46 is also used to contact other transistors (not shown). In the case of the p-well tie-down and n-well tie-down, Vbb and Vcc interconnections 50 and 52, respectively, are formed over and in electrical contact with conductive material 46 to connect the wells to their power supplies (not shown).
A problematic aspect of the assembly described with reference to FIG. 1 is that a p-type region 54 has been formed within n-well tie-down region 18. P-type region 54 was formed when halo regions 34 were generated (as described below with reference to FIGS. 2-3), and forms a diode between n-type diffusion region 42 and an underlying n-well. Such diode can adversely affect electrical connection between conductively doped region 42 and the underlying n-well, and can thus adversely affect operation of an n-well tie-down.
A prior art method of forming NMOS transistor 25 and the n-well tie-down is described below with reference to FIGS. 2 and 3. Referring initially to FIG. 2, transistor gate 24 and spacers 26 have been formed over NMOS region 16, and mask material 41 (typically photoresist) has been formed over n-well tie-down region 18. Further, an opening 60 has been formed through material 41 to expose underlying substrate 11 in the n-well region. A p-type dopant 62 is angle implanted into regions 16 and 18 to form diffusion regions 34 and 54.
Also shown in FIG. 2 is an n-type dopant 68 being implanted into regions 16 and 18 to form NMOS source/drain regions 30 and n-well tie-down 42. It is noted that the p-type implant, when done after provision of spacers, can be placed inside the n-type doped region or deeper, but after diffusion due to heat steps will likely end up deeper than an n+ region because of the faster diffusion of boron (a common p-type dopant) than the n-type dopants. For instance, FIG. 3 illustrates wafer fragment 10 after it has been subjected to thermal processing. Such thermal processing diffuses the p-type dopant ahead of the n-type dopant. It would be desirable to develop alternative methods of forming n-well type tie-down regions which avoid the formation of p-type diffusion regions within the n-well tie-down.
In one aspect, the invention includes a semiconductor processing method. A semiconductive material is provided. The semiconductive material has a first portion and a second portion. The first portion is a p-type doped portion and the second portion is an n-type doped portion. A mask material is formed over the p-type and n-type doped portions. A first opening is formed to extend through the mask material and to the n-type doped region. A second opening is formed to extend through the mask material and to the p-type doped region. Conductively doped polysilicon is formed within the first and second openings. Dopant is out-diffused from the conductively-doped polysilicon and into the n-type and p-type doped portions.
In another aspect, the invention includes a method of forming a CMOS construction. A semiconductive material is provided. The semiconductive material has a first portion and a second portion. The first portion is a p-type doped portion and the second portion is an n-type doped portion. A PMOS transistor location of the second portion is defined, an n-well tie-down location of the second portion is defined, and an NMOS transistor location of the first portion is defined. A first transistor gate is formed over the NMOS transistor location of the first portion, and a second transistor gate is formed over the PMOS transistor location of the second portion. A mask material is formed over the semiconductive material. The mask material covers the n-well tie-down location and PMOS transistor location of the second portion. The mask material has a first opening extending therethrough to the NMOS transistor location of the first portion, and p-type dopant is implanted through the first opening and into the NMOS transistor location. A second opening is formed to extend through the mask material and to the n-well tie-down location. Polysilicon (which is heavily doped with an n-type dopant) is provided within the first and second openings. N-type dopant is out-diffused from the conductively-doped polysilicon into both the n-well tie-down location and the NMOS transistor location.